1. Field of the Invention
The present invention relates to the field of integrated circuits; more specifically, it relates to architecture for integrated circuits containing voltage islands.
2. Background of the Invention
Designing application specific integrated circuits (ASICs) and system-on-chips (SOCs) entails selecting several different designs selected from a library of designs and inserting them in a basic framework of inputs, output and power supplies. However, integrated circuit manufacturing techniques have progressed to the point where advanced ASIC and SOC integration complexity create serious problems related to the distribution of power to the cores of ASIC or SOC devices.
Some cores may be selectively powered up or down or even powered at voltages that are different from other core voltages. For example, analog cores, embedded field programmable gate arrays (eFPGA) and embedded dynamic random access memory (DRAM) cores require higher minimum voltages to function than, for example, digital complementary metal-oxide-silicon (CMOS) logic cores. In some cases, it might be advantageous to run a core at a higher voltage to increase performance. Also, some applications (e.g. battery power supplies) are sensitive to the power consumed by leakage currents in non-switching circuits within a core.
However, as orders of integration of ASIC and SOC devices becomes ever more complex, even cores themselves have internal power consumption and power distribution problems that hereto have remained un-resolved. Therefore, there is a need for a technique to resolve intra-core power consumption and power distribution problems.